This invention relates generally to a memory module for an information processing system and, in particular, to a memory module having selectable operating modes including a selectable data bus width and a selectable memory device control signal generation.
A memory module for an information processing system typically includes a substrate, such as a printed circuit board, a plurality of memory device integrated circuits, such as dynamic random access memories (DRAMS), and associated logic for generating memory timing and control signals, latching data, etc. One or more of the memory modules are coupled to a system bus of an information processing system and provide storage of data and instructions for one or more central processing units (CPUs) which are also coupled to the system bus. In some systems the memory module(s) may be coupled to the system bus via a memory bus and a memory control unit (MCU), the MCU being interposed between the system bus and the memory bus.
The system bus normally includes a data bus having a predetermined number of signal lines for defining a width of the bus. For example, a data bus may have 8, 16, 32, 64 or more signal lines for conveying an equal number of data bits. Modern, high performance systems are generally characterized by a data bus width of 64 bits (double-word) or 128 bits (quad-word).
The system bus normally also includes an address bus for defining data storage address locations within the memory module(s). The number of signal lines which comprise the address bus is directly related to the number of address storage locations which may be directly addressed by the the bus. For example, 20 address signal lines can directly address approximately one million address locations. Modern systems may have 28 or more address signal lines. For some system bus architectures the address bus is provided as a discrete bus while for other types of systems the address bus is time shared, or multiplexed, with all or a portion of the data bus. For these latter type of systems the multiplexed signal lines can convey an address during a first portion of a system bus cycle and convey data relating to the address during a second portion of the system bus cycle.
The system bus typically also includes a number of control signal lines such as memory read and write strobes, clock and bus cycle timing signal lines, etc.
Conventional practice in the design and manufacture of memory modules is to provide a module suitable for use with only one system bus or memory bus configuration. That is, the memory module is designed to accommodate a fixed data bus width, such as 64 or 128 bits. It can be appreciated that if a manufacturer of information processing systems provides different types of systems having different data bus widths that a memory module having a fixed bus width would not be useable in two or more different types of systems.
Also, DRAM devices are available in a number of operating configurations including page mode and static column mode. During a conventional page mode access cycle a row address is applied to the device, a row address strobe (RAS*) signal is asserted, a column address is applied and a column address strobe (CAS*) signal is asserted such that a particular address location within the DRAM is selected. The device is repetitively accessed in the page mode by incrementing the column address and reasserting CAS* without incurring the overhead of also changing the row address and reasserting RAS*. Thus, a conventional page mode type of DRAM page mode operation includes repetitive assertions of CAS*.
In a static column type of device the DRAM includes circuitry which detects transitions of the column address signals. With this type of device the requirement of repetitively asserting CAS* is eliminated in that applying a new column address, with CAS* remaining asserted, is sufficient to initiate a device read or write access cycle to the selected address. In general, static column operation results in a faster access cycle in that set-up and hold times associated with CAS* are eliminated.
As can be appreciated, these two types of DRAM devices have differing timing and control signal generation requirements which generally preclude conventional memory modules from operating with both types of devices. That is, conventional memory modules are typically designed to work with one type of device or the other. In that DRAM devices are in great demand and adequate supplies of a given type of device are not always readily available it can be seen that a memory module having the ability to operate with more than one type of DRAM device without modification is a desirable feature.
The foregoing and other problems are overcome and other advantages are realized by a memory unit, constructed and operated in accordance with the invention, for storing information units and being interconnected during operation with a memory control unit. The memory unit includes a bus coupling the memory unit to the memory control unit by a plurality of signal lines. The memory unit further includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.
Each of the memory planes further has an associated counter for storing and incrementing a portion of a column address, the counters being responsive to a bus signal asserted by the memory control unit. Up to 256 double-word write accesses or up to 128 quad-word read accesses can be achieved by supplying an initial address and thereafter toggling the bus signal to increment the counters. For page mode type of DRAMs toggling the bus signal also results in a deassertion and a reassertion of the CAS signal. For static column type of DRAMs the transition of the address counter outputs is sufficient to cause the DRAMs to begin a new access cycle.
The memory unit of the invention furthermore provides status signals to the memory control unit including a match signal to indicate that a particular memory unit lies within a range of addresses associated with a provided address and a signal which indicates, when asserted, that static column type of DRAMs are installed upon the memory unit asserting the match signal.